1. Field of the Invention
The present invention is related to a device for generating a test pattern of a memory chip and method thereof, and particularly to a device that utilizes simple logic circuits to simplify generation of a test pattern of a memory chip and method thereof.
2. Description of the Prior Art
In the newest generation structures (open-bit line structures 6F2, 8F2) of dynamic random access memory, because memory cells of the open-bit line structures 6F2, 8F2 are smaller, arrangement of the memory cells is more compact and each cell may receive more noise from adjacent memory cells.
Because unit area of the DRAM with open-bit line structures 6F2, 8F2 has more memory cells, it is difficult to write a correct test pattern to the DRAM with open-bit line structures 6F2, 8F2, such that reduction of test bit cost of the memory chip becomes a significant issue for a designer. In the prior art, no simple test method can write a solid pattern, a checkerboard pattern, a row bar pattern, and a column bar pattern to the memory chip. Therefore, it is difficult to reduce the test bit cost of the memory chip by utilizing the test method of the prior art.